U1AFS600-2FG256YI
| Model | U1AFS600-2FG256YI |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
DC and Power Characteristics
RAM Dynamic Contribution—P
MEMORY
Operating Mode
P
MEMORY
= (N
BLOCKS
* PAC11 *
β
2
* F
READ-CLOCK
) + (N
BLOCKS
* PAC12 *
β
3
* F
WRITE-CLOCK
)
N
BLOCKS
is the number of RAM blocks used in the design.
F
READ-CLOCK
is the memory read clock frequency.
β
2
is the RAM enable rate for read operations—guidelines are provided in
β
3
the RAM enable rate for write operations—guidelines are provided in
F
WRITE-CLOCK
is the memory write clock frequency.
Standby Mode and Sleep Mode
P
MEMORY
= 0 W
PLL/CCC Dynamic Contribution—P
PLL
Operating Mode
P
PLL
= PAC13 * F
CLKOUT
F
CLKIN
is the input clock frequency.
F
CLKOUT
is the output clock frequency.
1
Standby Mode and Sleep Mode
P
PLL
= 0 W
Nonvolatile Memory Dynamic Contribution—P
NVM
Operating Mode
The NVM dynamic power consumption is a piecewise linear function of frequency.
P
NVM
= N
NVM-BLOCKS
*
β
4
*(PAC16 + PAC17 * F
READ-NVM
when F
READ-NVM
> 33 MHz
N
NVM-BLOCKS
is the number of NVM blocks used in the design (2 inAFS600).
F
READ-NVM
is the NVM read clock frequency.
Standby Mode and Sleep Mode
P
NVM
= 0 W
P
NVM
= N
NVM-BLOCKS
*
β
4
* PAC15 * F
READ-NVM
when F
READ-NVM
≤
33 MHz,
β
4
is the NVM enable rate for read operations. Default is 0 (NVM mainly in idle state).
Crystal Oscillator Dynamic Contribution—P
XTL-OSC
Operating Mode
P
XTL-OSC
= PAC18
Standby Mode
P
XTL-OSC
= PAC18
Sleep Mode
P
XTL-OSC
= 0 W
1.
The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the
PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output
clock in the formula output clock by adding its corresponding contribution (P
AC14
* F
CLKOUT
product) to the total PLL
contribution.
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R e visio n 3
