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U1AFS600-2FG256YI

U1AFS600-2FG256YI

Model U1AFS600-2FG256YI
Description Field Programmable Gate Array,
PDF file Total 334 pages (File size: 18M)
Chip Manufacturer MICROSEMI
Fusion Family of Mixed Signal FPGAs
Table 2-109 •
3.3 V LVTTL / 3.3 V LVCMOS High Slew
Commercial Temperature Range Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V
Applicable to Standard I/Os
Drive
Strength
2 mA
Speed
Grade
Std.
–1
–2
2
4 mA
Std.
–1
–2
6 mA
Std.
–1
–2
8 mA
Std.
–1
–2
t
DOUT
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
t
DP
7.07
6.01
5.28
7.07
6.01
5.28
4.41
3.75
3.29
4.41
3.75
3.29
t
DIN
0.04
0.04
0.03
0.04
0.04
0.03
0.04
0.04
0.03
0.04
0.04
0.03
t
PY
1.00
0.85
0.75
1.00
0.85
0.75
1.00
0.85
0.75
1.00
0.85
0.75
t
EOUT
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
t
ZL
7.20
6.12
5.37
7.20
6.12
5.37
4.49
3.82
3.36
4.49
3.82
3.36
t
ZH
6.23
5.30
4.65
6.23
5.30
4.65
3.75
3.19
2.80
3.75
3.19
2.80
t
LZ
2.07
1.76
1.55
2.07
1.76
1.55
2.39
2.04
1.79
2.39
2.04
1.79
t
HZ
2.15
1.83
1.60
2.15
1.83
1.60
2.69
2.29
2.01
2.69
2.29
2.01
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
For the derating values at specific junction temperature and voltage supply levels, refer to
Revision 3
2- 183
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