U1AFS600-2FG256YI
| Model | U1AFS600-2FG256YI |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
2.5 V GTL+
Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential
amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V.
Table 2-147 •
Minimum and Maximum DC Input and Output Levels
2.5 V
GTL+
Drive
Strength
33 mA
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
VIL
Min.
V
–0.3
Max.
V
VIH
Min.
V
Max.
V
3.6
VOL
Max.
V
0.6
VOH
Min.
V
–
IOL
mA
33
IOH
mA
33
IOSL
Max.
mA
3
124
IOSH
Max.
mA
3
169
IIL
1
IIH
2
µA
4
µA
4
10
10
VREF – 0.1 VREF + 0.1
VTT
GTL+
Test Point
10 pF
25
Figure 2-127 •
AC Loading
Table 2-148 •
AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
VREF – 0.1
Input High (V)
VREF + 0.1
Measuring Point* (V)
1.0
VREF (typ.) (V)
1.0
VTT (typ.) (V)
1.5
C
LOAD
(pF)
10
Note:
*Measuring point = Vtrip. See
for a complete table of trip points.
Timing Characteristics
Table 2-149 •
2.5 V GTL+
Commercial Temperature Range Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 2.3 V, VREF = 1.0 V
Speed
Grade
Std.
–1
–2
t
DOUT
0.66
0.56
0.49
t
DP
2.21
1.88
1.65
t
DIN
0.04
0.04
0.03
t
PY
1.51
1.29
1.13
t
EOUT
0.43
0.36
0.32
t
ZL
2.25
1.91
1.68
t
ZH
2.10
1.79
1.57
t
LZ
t
HZ
t
ZLS
4.48
3.81
3.35
t
ZHS
4.34
3.69
4.34
Units
ns
ns
ns
Note:
For the derating values at specific junction temperature and voltage supply levels, refer to
Revision 3
2- 205
