U1AFS600-2FG256YI
| Model | U1AFS600-2FG256YI |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Device Architecture
1.00E-0.3
RC Time Constant Values vs. Frequency
RC Time Constant (sec)
1.00E-0.4
1.00E-0.5
1.00E-0.6
1.00E-0.7
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Frequency (MHz)
Figure 2-18 •
Crystal Oscillator: RC Time Constant Values vs. Frequency (typical)
Table 2-10 •
XTLOSC Signals Descriptions
Signal Name
XTL_EN*
XTL_MODE*
Width
1
2
Direction
Function
Enables the crystal. Active high.
Settings for the crystal clock for different frequency.
Value
b'00
b'01
b'10
b'11
SELMODE
1
IN
Modes
RC network
Low gain
Medium gain
High gain
Frequency Range
32 KHz to 4 MHz
32 to 200 KHz
0.20 to 2.0 MHz
2.0 to 20.0 MHz
Selects the source of XTL_MODE and also enables the
XTL_EN. Connect from RTCXTLSEL from AB.
0
For normal operation or sleep mode, XTL_EN
depends on FPGA_EN, XTL_MODE depends on
MODE
For Standby mode, XTL_EN is
XTL_MODE depends on RTC_MODE
enabled,
1
RTC_MODE[1:0]
MODE[1:0]
2
2
IN
IN
Settings for the crystal clock for different frequency ranges.
XTL_MODE uses RTC_MODE when SELMODE is '1'.
Settings for the crystal clock for different frequency ranges.
XTL_MODE uses MODE when SELMODE is '0'. In Standby,
MODE inputs will be 0's.
0 when 1.5 V is not present for VCC 1 when 1.5 V is present
for VCC
Crystal Clock source
Crystal Clock output
FPGA_EN*
XTL
CLKOUT
1
1
1
IN
IN
OUT
Note:
*Internal signal—does not exist in macro.
2- 22
R e visio n 3
