U1AFS600-2FG256YI
| Model | U1AFS600-2FG256YI |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
Standard Conversion
t
SAMPLE1
t
DATA2START3
SYSCLK
t
SUADCSTART
t
HDADCSTART
ADCSTART
t
CK2QBUSY
BUSY
t
CK2QSAMPLE
SAMPLE
t
CONV2
t
CK2QVAL
t
CK2QVAL
DATAVALID
t
CLK2RESULT
ADC_RESULT[11:0]
1
st
Sample Result
2
nd
Sample Result
Notes:
1. Refer to
for the calculation on the sample time, t
SAMPLE
.
2. See
for calculation of the conversion time, t
CONV
.
3. Minimum time to issue an ADCSTART after DATAVALID is 1 SYSCLK period
Figure 2-91 •
Standard Conversion Status Signal Timing Diagram
Intra-Conversion
SYSCLK
ADCRESET
ADCSTART
t
CK2QBUSY
BUSY
t
CK2QSAMPLE
SAMPLE
t
CLR2QVAL
DATAVALID
t
CK2QCAL
CALIBRATE
Interrupts Power-Up Calibration
Resumes Power-Up Calibration
t
CK2QCAL
t
CONV
*
t
CK2QVAL
t
CK2QSAMPLE
Note:
*t
CONV
represents the conversion time of the second conversion. See
for calculation of the
conversion time, t
CONV
.
Figure 2-92 •
Intra-Conversion Timing Diagram
Revision 3
2- 115
