• Inventory
  • Products
  • Technical Information
  • Circuit Diagram
  • Data Sheet
Data Sheet
Home > Data Sheet > U1AFS600-2FG256YI
U1AFS600-2FG256YI

U1AFS600-2FG256YI

Model U1AFS600-2FG256YI
Description Field Programmable Gate Array,
PDF file Total 334 pages (File size: 18M)
Chip Manufacturer MICROSEMI
Device Architecture
Table 2-52 •
Calibrated Analog Channel Accuracy
1,2,3
Worst-Case Industrial Conditions, T
J
= 85°C
Condition
Analog
Pad
AV, AC
Prescaler Range (V)
Positive Range
16
8
4
2
1
AT
16
4
Negative Range
AV, AC
16
8
4
2
1
Notes:
1. Channel Accuracy includes prescaler and ADC accuracies. For 12-bit mode, multiply the LSB count by 4. For 8-bit
mode, divide the LSB count by 4. Overall accuracy remains the same.
2. Requires enabling Analog Calibration using SmartGen Analog System Builder. For further details, refer to the
"Temperature, Voltage, and Current Calibration in Fusion FPGAs" chapter of the
3. Calibrated with two-point calibration methodology, using 20% and 80% full-scale points.
4. The lower limit of the input voltage is determined by the prescaler input offset.
Total Channel Error (LSB)
Negative Max.
–6
–6
–7
–7
–6
–5
–7
–7
–7
–7
–7
–16
Median
1
0
–1
0
–1
0
–1
ADC in 10-Bit Mode
1
–1
–2
–2
–1
Positive Max.
6
6
7
7
6
5
7
9
7
9
7
20
Input Voltage
4
(V)
0.300 to 12.0
0.250 to 8.00
0.200 to 4.00
0.150 to 2.00
0.050 to 1.00
0.300 to 16.0
0.100 to 4.00
–0.400 to –10.5
–0.350 to –8.00
–0.300 to –4.00
–0.250 to –2.00
–0.050 to –1.00
ADC in 10-Bit Mode
2- 12 6
R e visio n 3
Go Upload

* Only PDF files are allowed for upload

* Enter up to 200 characters.