U1AFS600-2FG256YI
| Model | U1AFS600-2FG256YI |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
P
S-CELL
= 0 W
P
C-CELL
= 0 W
P
NET
= 0 W
P
LOGIC
= 0 W
I/O Input and Output Buffer Contribution—P
I/O
This example uses LVTTL 3.3 V I/O cells. The output buffers are 12 mA–capable, configured with high
output slew and driving a 35 pF output load.
F
CLK
= 50 MHz
Number of input pins used: N
INPUTS
= 30
Number of output pins used: N
OUTPUTS
= 40
Estimated I/O buffer toggle rate:
α
2
= 0.1 (10%)
Estimated IO buffer enable rate:
β
1
= 1 (100%)
Operating Mode
P
INPUTS
= N
INPUTS
* (
α
2
/ 2) * PAC9 * F
CLK
P
INPUTS
= 30 * (0.1 / 2) * 0.01739 * 50
P
INPUTS
= 1.30 mW
P
OUTPUTS
= N
OUTPUTS
* (
α
2
/ 2) *
β
1
* PAC10 * F
CLK
P
OUTPUTS
= 40 * (0.1 / 2) * 1 * 0.4747 * 50
P
OUTPUTS
= 47.47 mW
P
I/O
= P
INPUTS
+ P
OUTPUTS
P
I/O
= 1.30 mW + 47.47 mW
P
I/O
= 48.77 mW
Standby Mode and Sleep Mode
P
INPUTS
= 0 W
P
OUTPUTS
= 0 W
P
I/O
= 0 W
RAM Contribution—P
MEMORY
Frequency of Read Clock: F
READ-CLOCK
= 10 MHz
Frequency of Write Clock: F
WRITE-CLOCK
= 10 MHz
Number of RAM blocks: N
BLOCKS
= 20
Estimated RAM Read Enable Rate:
β
2
= 0.125 (12.5%)
Estimated RAM Write Enable Rate:
β
3
= 0.125 (12.5%)
Operating Mode
P
MEMORY
= (N
BLOCKS
* PAC11 *
β
2
* F
READ-CLOCK
) + (N
BLOCKS
* PAC12 *
β
3
* F
WRITE-CLOCK
)
P
MEMORY
= (20 * 0.025 * 0.125 * 10) + (20 * 0.030 * 0.125 * 10)
P
MEMORY
= 1.38 mW
Standby Mode and Sleep Mode
P
MEMORY
= 0 W
Revision 3
3- 29
