U1AFS600-2FG484
| Model | U1AFS600-2FG484 |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
To initiate a current measurement, the appropriate Current Monitor Strobe (CMSTB) signal on the AB
macro must be asserted low for at least t
CMSLO
in order to discharge the previous measurement. Then
CMSTB must be asserted high for at least t
CMSET
prior to asserting the ADCSTART signal. The CMSTB
must remain high until after the SAMPLE signal is de-asserted by the AB macro. Note that the minimum
sample time cannot be less than t
CMSHI
.
shows the timing diagram of CMSTB in relationship
with the ADC control signals.
t
CMSHI
CMSTBx
t
CMSLO
VADC
t
CMSET
ADCSTART can be asserted
after this point to start ADC
sampling.
ADCSTART
Figure 2-69 •
Timing Diagram for Current Monitor Strobe
illustrates positive current monitor operation. The differential voltage between AV and AC
goes into the 10× amplifier and is then converted by the ADC. For example, a current of 1.5 A is drawn
from a 10 V supply and is measured by the voltage drop across a 0.050
Ω
sense resistor, The voltage
drop is amplified by ten times by the amplifier and then measured by the ADC. The 1.5 A current creates
a differential voltage across the sense resistor of 75 mV. This becomes 750 mV after amplification. Thus,
the ADC measures a current of 1.5 A as 750 mV. Using an ADC with 8-bit resolution and VAREF of 2.56
V, the ADC result is decimal 75.
shows how to compute the current from the ADC result.
I
=
(
ADC
×
V
AREF
) ⁄ (
10
×
2
×
R
sense
)
EQ 3
where
I is the current flowing through the sense resistor
ADC is the result from the ADC
VAREF is the Reference voltage
N is the number of bits
Rsense is the resistance of the sense resistor
N
Revision 2
2- 89
Related PDFs
| Model | Description | Manufacturer | Operation |
|---|---|---|---|
 U1AFS600-2FG484YC
|
FPGA | MICROSEMI | Preview |
