U1AFS600-2FG484
Model | U1AFS600-2FG484 |
Description | Field Programmable Gate Array, |
PDF file | Total 334 pages (File size: 18M) |
Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
t
PY
t
PYS
PAD
D
Y
t
DIN
Q
DIN
To Array
CLK
t
PY
= MAX(t
PY
(R), t
PY
(F))
t
PYs
= MAX(t
PYS
(R), t
PYS
(F))
t
DIN
= MAX(t
DIN
(R), t
DIN
(F))
I/O interface
VIH
V
trip
V
trip
VCC
50%
Y
GND
t
PY
(R)
t
PYS
(R)
t
PY
(F)
t
PYS
(F)
VCC
50%
DIN
GND
t
DIN
(R)
t
DIN
(F)
50%
50%
PAD
VIL
Figure 2-114 •
Input Buffer Timing Model and Delays (example)
Revision 2
2- 163