U1AFS600-2FG484
| Model | U1AFS600-2FG484 |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Device Architecture
CLK
t
DDROSUD2
t
DDROHD2
Data_F
1
2
t
DDROSUD1
Data_R 6
7
t
DDROHD1
8
9
10
t
DDRORECCLR
CLR
t
DDROREMCLR
t
DDROCLR2Q
Out
t
DDROCLKQ
7
2
8
3
9
4
10
11
3
4
5
Figure 2-143 •
Output DDR Timing Diagram
Timing Characteristics
Table 2-182 •
Output DDR Propagation Delays
Commercial Temperature Range Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V
Parameter
t
DDROCLKQ
t
DDROSUD1
t
DDROSUD2
t
DDROHD1
t
DDROHD2
t
DDROCLR2Q
t
DDROREMCLR
t
DDRORECCLR
t
DDROWCLR1
t
DDROCKMPWH
t
DDROCKMPWL
F
DDOMAX
Description
Clock-to-Out of DDR for Output DDR
Data_F Data Setup for Output DDR
Data_R Data Setup for Output DDR
Data_F Data Hold for Output DDR
Data_R Data Hold for Output DDR
Asynchronous Clear-to-Out for Output DDR
Asynchronous Clear Removal Time for Output DDR
Asynchronous Clear Recovery Time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width High for the Output DDR
Clock Minimum Pulse Width Low for the Output DDR
Maximum Frequency for the Output DDR
–2
0.70
0.38
0.38
0.00
0.00
0.80
0.00
0.22
0.22
0.36
0.32
1,048
–1
0.80
0.43
0.43
0.00
0.00
0.91
0.00
0.25
0.25
0.41
0.37
1,232
Std.
0.94
0.51
0.51
0.00
0.00
1.07
0.00
0.30
0.30
0.48
0.43
1,404
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
Note:
For the derating values at specific junction temperature and voltage supply levels, refer to
2- 22 4
R e visio n 2
Related PDFs
| Model | Description | Manufacturer | Operation |
|---|---|---|---|
 U1AFS600-2FG484YC
|
FPGA | MICROSEMI | Preview |
