U1AFS600-2FG484
| Model | U1AFS600-2FG484 |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
RC Oscillator Dynamic Contribution—P
RC-OSC
Operating Mode
P
RC-OSC
= PAC19
Standby Mode and Sleep Mode
P
RC-OSC
= 0 W
Analog System Dynamic Contribution—P
AB
Operating Mode
P
AB
= PAC20
Standby Mode and Sleep Mode
P
AB
= 0 W
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the
toggle rate of a net is 100%, this means that the net switches at half the clock frequency. Below are some
examples:
•
•
The average toggle rate of a shift register is 100%, as all flip-flop outputs toggle at half of the clock
frequency.
The average toggle rate of an 8-bit counter is 25%:
–
–
–
–
–
–
Bit 0 (LSB) = 100%
Bit 1 = 50%
Bit 2 = 25%
…
Bit 7 (MSB) = 0.78125%
Average toggle rate = (100% + 50% + 25% + 12.5% + . . . 0.78125%) / 8.
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled. When
non-tristate output buffers are used, the enable rate should be 100%.
Table 3-16 •
Toggle Rate Guidelines Recommended for Power Calculation
Component
Definition
Toggle rate of VersaTile outputs
I/O buffer toggle rate
Guideline
10%
10%
α
1
α
2
Component
Table 3-17 •
Enable Rate Guidelines Recommended for Power Calculation
Definition
I/O output buffer enable rate
RAM enable rate for read operations
RAM enable rate for write operations
NVM enable rate for read operations
Guideline
100%
12.5%
12.5%
0%
β
1
β
2
β
3
β
4
Revision 2
3- 27
Related PDFs
| Model | Description | Manufacturer | Operation |
|---|---|---|---|
 U1AFS600-2FG484YC
|
FPGA | MICROSEMI | Preview |
