U1AFS600-2FG484
| Model | U1AFS600-2FG484 |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Device Architecture
Modes of Operation
Standby Mode
Standby mode allows periodic power-up and power-down of the FPGA fabric. In standby mode, the real-
time counter and crystal block are ON. The FPGA is not powered by disabling the 1.5 V voltage
regulator. The 1.5 V voltage regulator can be enabled when the preset count is matched. Refer to the
for details. To enter standby mode, the RTC must be first
configured and enabled. Then VRPSM is shut off by deasserting the VRPU signal. The 1.5 V voltage
regulator is then disabled, and shuts off the 1.5 V output.
Sleep Mode
In sleep mode, the real-time counter and crystal blocks are OFF. The 1.5 V voltage regulator inside the
VRPSM can only be enabled by the PUB or TRST pin. Refer to the
for details on power-up and power-down of the 1.5 V
voltage regulator.
Standby and Sleep Mode Circuit Implementation
For extra power savings, VJTAG and VPUMP should be at the same voltage as VCC, floated or ground,
during standby and sleep modes. Note that when VJTAG is not powered, the 1.5 V voltage regulator
cannot be enabled through TRST.
VPUMP and VJTAG can be controlled through an external switch. Microsemi recommends ADG839,
ADG849, or ADG841 as possible switches.
shows the implementation for controlling
VPUMP. The IN signal of the switch can be connected to PTBASE of the Fusion device. VJTAG can be
controlled in same manner.
3.3 V
VPUMP (or JTAG) Supply
Fusion
S
IN
PTBASE
External
Pass
Transistor
2N2222
ADG841
VPUMP (or JTAG)
Pin of Fusion
PTEM
1.5 V
Figure 2-28 •
Implementation to Control VPUMP
2- 34
R e visio n 2
Related PDFs
| Model | Description | Manufacturer | Operation |
|---|---|---|---|
 U1AFS600-2FG484YC
|
FPGA | MICROSEMI | Preview |
