U1AFS600-2FG484
| Model | U1AFS600-2FG484 |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
Differential I/O Characteristics
Configuration of the I/O modules as a differential pair is handled by the Microsemi Designer
software when the user instantiates a differential I/O macro in the design.
Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output
Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no
support for bidirectional I/Os or tristates with these standards.
LVDS
Low-Voltage Differential Signal (ANSI/TIA/EIA-644) is a high-speed differential I/O standard. It requires
that one data bit be carried through two signal lines, so two pins are needed. It also requires external
resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in
The building blocks of the LVDS transmitter–receiver are one transmitter macro, one receiver macro,
three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three
driver resistors are different from those used in the LVPECL implementation because the output standard
specifications are different.
Bourns Part Number: CAT16-LV4F12
OUTBUF_LVDS
FPGA
P
165
Ω
ZO = 50
Ω
140
Ω
N
165
Ω
ZO = 50
Ω
100
Ω
N
P
FPGA
+
–
INBUF_LVDS
Figure 2-132 •
LVDS Circuit Diagram and Board-Level Implementation
Table 2-168 •
Minimum and Maximum DC Input and Output Levels
DC Parameter
VCCI
VOL
VOH
IOL
1
IOH
1
VI
IIL
2,3
IIH
2,4
VODIFF
VOCM
VICM
VIDIFF
Notes:
1.
2.
3.
4.
IOL/IOH defined by VODIFF/(Resistor Network)
Currents are measured at 85°C junction temperature.
IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
Description
Supply Voltage
Output Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Voltage
Input Low Voltage
Input High Voltage
Differential Output Voltage
Output Common Mode Voltage
Input Common Mode Voltage
Input Differential Voltage
Min.
2.375
0.9
1.25
0.65
0.65
0
Typ.
2.5
1.075
1.425
0.91
0.91
Max.
2.625
1.25
1.6
1.16
1.16
2.925
10
10
Units
V
V
V
mA
mA
V
μA
μA
mV
V
V
mV
250
1.125
0.05
100
350
1.25
1.25
350
450
1.375
2.35
Revision 2
2- 211
Related PDFs
| Model | Description | Manufacturer | Operation |
|---|---|---|---|
 U1AFS600-2FG484YC
|
FPGA | MICROSEMI | Preview |
