U1AFS600-2FG484
| Model | U1AFS600-2FG484 |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Device Architecture
Table 2-7 •
AFS250 Global Resource Timing
Commercial Temperature Range Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V
–2
Parameter
t
RCKL
t
RCKH
t
RCKMPWH
t
RCKMPWL
t
RCKSW
F
RMAX
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For the derating values at specific junction temperature and voltage supply levels, refer to
–1
Min.
1
1.02
1.00
Max.
2
1.27
1.30
Std.
Min.
1
1.20
1.17
Max.
2
Units
1.50
1.53
ns
ns
ns
ns
Description
Input Low Delay for Global Clock
Input High Delay for Global Clock
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
Min.
1
0.89
0.88
Max.
2
1.12
1.14
0.26
0.30
0.35
ns
MHz
Table 2-8 •
AFS090 Global Resource Timing
Commercial Temperature Range Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V
–2
Parameter
t
RCKL
t
RCKH
t
RCKMPWH
t
RCKMPWL
t
RCKSW
F
RMAX
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For the derating values at specific junction temperature and voltage supply levels, refer to
–1
Max.
2
1.07
1.10
Min.
1
0.96
0.95
Std.
Max.
2
Min.
1
1.21
1.25
1.13
1.12
Max.
2
1.43
1.47
Units
ns
ns
ns
ns
Description
Input Low Delay for Global Clock
Input High Delay for Global Clock
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
Min.
1
0.84
0.83
0.27
0.30
0.36
ns
MHz
2- 18
R e visio n 2
Related PDFs
| Model | Description | Manufacturer | Operation |
|---|---|---|---|
 U1AFS600-2FG484YC
|
FPGA | MICROSEMI | Preview |
