U1AFS600-2FG484
| Model | U1AFS600-2FG484 |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
Static Power Consumption of Various Internal Resources
Table 3-15 •
Different Components Contributing to the Static Power Consumption in Fusion Devices
Parameter
PDC1
PDC2
PDC3
PDC4
PDC5
PDC6
PDC7
PDC8
PDC9
Definition
Core static power contribution in
operating mode
Power
Supply
VCC
1.5 V
3.3 V
3.3 V
1.5 V
3.3 V
3.3 V
Device-Specific Static Contributions
AFS1500 AFS600 AFS250 AFS090 Units
18
7.5
0.66
0.03
1.19
8.25
3.3
See
See
1.5 V
2.55
mW
4.50
3.00
mW
mW
mW
mW
mW
mW
Device static power contribution in VCC33A
standby mode
Device static power contribution in VCC33A
sleep mode
NVM static power contribution
Analog
Block
static
contribution of ADC
Analog
Block
static
contribution per Quad
VCC
power VCC33A
power VCC33A
VCCI
VCCI
VCC
Static contribution per input pin –
standard dependent contribution
Static contribution per input pin –
standard dependent contribution
Static contribution for PLL
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more
accurate and detailed power estimations, use the SmartPower tool in the Libero IDE software.
The power calculation methodology described below uses the following variables:
•
•
•
•
•
•
•
•
•
•
•
The number of PLLs as well as the number and the frequency of each output clock generated
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
The number of NVM blocks used in the design
The number of Analog Quads used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in
Enable rates of output buffers—guidelines are provided for typical applications in
Read rate and write rate to the RAM—guidelines are provided for typical applications in
Read rate to the NVM blocks
The calculation should be repeated for each clock domain defined in the design.
Revision 2
3- 23
Related PDFs
| Model | Description | Manufacturer | Operation |
|---|---|---|---|
 U1AFS600-2FG484YC
|
FPGA | MICROSEMI | Preview |
