U1AFS600-2FG484
| Model | U1AFS600-2FG484 |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Device Architecture
Flash Memory Block Pin Names
Table 2-19 •
Flash Memory Block Pin Names
Interface Name
ADDR[17:0]
AUXBLOCK
BUSY
CLK
DATAWIDTH[1:0]
Width Direction
18
1
1
1
2
In
In
Out
In
In
Description
Byte offset into the FB. Byte-based address.
When asserted, the page addressed is used to access the auxiliary
block within that page.
When asserted, indicates that the FB is performing an operation.
User interface clock. All operations and status are synchronous to the
rising edge of this clock.
Data width
00 = 1 byte in RD/WD[7:0]
01 = 2 bytes in RD/WD[15:0]
1x = 4 bytes in RD/WD[31:0]
DISCARDPAGE
ERASEPAGE
1
1
In
In
When asserted, the contents of the Page Buffer are discarded so that
a new page write can be started.
When asserted, the address page is to be programmed with all zeros.
ERASEPAGE must transition synchronously with the rising edge of
CLK.
When asserted, indicates to the JTAG controller that the FPGA
interface is accessing the FB.
When asserted, the page addressed is overwritten with the contents of
the Page Buffer if the page is writable.
When asserted, all program operations will set the overwrite protect bit
of the page being programmed.
When asserted with REN, initiates a read page status operation.
When asserted, a modified Page Buffer must be programmed or
discarded before accessing a new page.
Adds a pipeline stage to the output for operation above 50 MHz.
When asserted, writes the contents of the Page Buffer into the FB
page addressed.
Read data; data will be valid from the first non-busy cycle (BUSY = 0)
after REN has been asserted.
When asserted with REN, initiates a read-next operation.
When asserted, initiates a read operation.
When asserted, resets the state of the FB (active low).
When asserted, the sector addressed is used to access the spare
page within that sector.
LOCKREQUEST
OVERWRITEPAGE
OVERWRITEPROTECT
PAGESTATUS
PAGELOSSPROTECT
PIPE
PROGRAM
RD[31:0]
READNEXT
REN
RESET
SPAREPAGE
1
1
1
1
1
1
1
32
1
1
1
1
In
In
In
In
In
In
In
Out
In
In
In
In
2- 42
R e visio n 2
Related PDFs
| Model | Description | Manufacturer | Operation |
|---|---|---|---|
 U1AFS600-2FG484YC
|
FPGA | MICROSEMI | Preview |
