U1AFS600-2FG484
| Model | U1AFS600-2FG484 |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
DDR Module Specifications
Input DDR Module
Input DDR
A
Data
INBUF
FF1
D
Out_QF
(to core)
CLK
CLKBUF
B
FF2
E
Out_QR
(to core)
CLR
INBUF
C
DDR_IN
Figure 2-140 •
Input DDR Timing Model
Table 2-179 •
Parameter Definitions
Parameter Name
t
DDRICLKQ1
t
DDRICLKQ2
t
DDRISUD
t
DDRIHD
t
DDRICLR2Q1
t
DDRICLR2Q2
t
DDRIREMCLR
t
DDRIRECCLR
Parameter Definition
Clock-to-Out Out_QR
Clock-to-Out Out_QF
Data Setup Time of DDR Input
Data Hold Time of DDR Input
Clear-to-Out Out_QR
Clear-to-Out Out_QF
Clear Removal
Clear Recovery
Measuring Nodes (from, to)
B, D
B, E
A, B
A, B
C, D
C, E
C, B
C, B
Revision 2
2- 221
Related PDFs
| Model | Description | Manufacturer | Operation |
|---|---|---|---|
 U1AFS600-2FG484YC
|
FPGA | MICROSEMI | Preview |
