Home > Data Sheet > U1AFS600-2FG484

U1AFS600-2FG484

Model	U1AFS600-2FG484
Description	Field Programmable Gate Array,
PDF file	Total 334 pages (File size: 18M)
Chip Manufacturer	MICROSEMI

Download (18M)

Datasheet Information

Revision

v2.0, Revision 1

(continued)

Changes

The

"Real-Time Counter (part of AB macro)" section

was updated significantly.

Please review carefully.

There was a typo in

Table 2-19 • Flash Memory Block Pin Names

for the

ERASEPAGE description; it was the same as DISCARDPAGE. As as a result, the

ERASEPAGE description was updated.

The t

FMAXCLKNVM

parameter was updated in

Table 2-25 • Flash Memory Block

Timing.

Table 2-31 • RAM4K9

and

Table 2-32 • RAM512X18

were updated.

Table 2-36 • Analog Block Pin Description,

the Function description for PWRDWN

was changed from "Comparator power-down if 1"

"ADC comparator power-down if 1. When asserted, the ADC will stop functioning,

and the digital portion of the analog block will continue operating. This may result in

invalid status flags from the analog block. Therefore, Microsemi does not

recommend asserting the PWRDWN pin."

Figure 2-73 • Gate Driver Example

was updated.

The

"ADC Operation" section

was updated. Please review carefully.

Figure 2-90 • Intra-Conversion Timing Diagram

and

Figure 2-91 • Injected

Conversion Timing Diagram

are new.

The

"Typical Performance Characteristics" section

is new.

Table 2-49 • Analog Channel Specifications

was significantly updated.

Table 2-50 • ADC Characteristics in Direct Input Mode

was significantly updated.

Table 2-52 • Calibrated Analog Channel Accuracy

1,2,3

, note 2 was updated.

Table 2-53 • Analog Channel Accuracy: Monitoring Standard Positive Voltages,

note 1 was updated.

Table 2-54 • ACM Address Decode Table for Analog Quad,

bit 89 was removed.

The data in the 2.5 V LCMOS and LVCMOS 2.5 V / 5.0 V rows were updated in

Table 2-75 • Fusion Standard and Advanced I/O – Hot-Swap and 5 V Input Tolerance

Capabilities.

Table 2-78 • Fusion Standard I/O Standards—OUT_DRIVE Settings,

LVCMOS

1.5 V, for OUT_DRIVE 2, was changed from a dash to a check mark.

The

"VCC15A Analog Power Supply (1.5 V)"

definition was changed from "A 1.5 V

analog power supply input should be used to provide this input"

"1.5 V clean analog power supply input for use by the 1.5 V portion of the analog

circuitry."

In the

"VCC33PMP Analog Power Supply (3.3 V)"

pin description, the following text

was changed from "VCC33PMP should be powered up before or simultaneously

with VCC33A"

"VCC33PMP should be powered up simultaneously with or after VCC33A."

The

"VCCOSC Oscillator Power Supply (3.3 V)" section

was updated to include

information about when to power the pin.

Page

5-4

R e vi s i o n 2

prev next

Related PDFs

Model	Description	Manufacturer	Operation
U1AFS600-2FG484YC	FPGA	MICROSEMI	Preview