U1AFS600-2FG484
| Model | U1AFS600-2FG484 |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Device Architecture
Refer to the
for a description of naming of global
pins.
JTAG Pins
Fusion devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any
voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to operate,
even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the Fusion
part must be supplied to allow JTAG signals to transition the Fusion device.
Isolating the JTAG power supply in a separate I/O bank gives greater flexibility with supply selection and
simplifies power supply and PCB design. If the JTAG interface is neither used nor planned to be used,
the VJTAG pin together with the TRST pin could be tied to GND.
TCK
Test Clock
Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-
up/-down resistor. If JTAG is not used, Microsemi recommends tying off TCK to GND or VJTAG through
a resistor placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired
state.
Note that to operate at all VJTAG voltages, 500
Ω
to 1 kΩ will satisfy the requirements. Refer to
for more information.
Table 2-183 •
Recommended Tie-Off Values for the TCK and TRST Pins
VJTAG
VJTAG at 3.3 V
VJTAG at 2.5 V
VJTAG at 1.8 V
VJTAG at 1.5 V
Notes:
1. Equivalent parallel resistance if more than one device is on JTAG chain.
2. The TCK pin can be pulled up/down.
3. The TRST pin can only be pulled down.
TDI
Test Data Input
Tie-Off Resistance
2, 3
200
Ω
to 1 kΩ
200
Ω
to 1 kΩ
500
Ω
to 1 kΩ
500
Ω
to 1 kΩ
Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor
on the TDI pin.
TDO
Test Data Output
Serial output for JTAG boundary scan, ISP, and UJTAG usage.
TMS
Test Mode Select
The TMS pin controls the use of the IEEE1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an
internal weak pull-up resistor on the TMS pin.
TRST
Boundary Scan Reset Pin
The TRST pin functions as an active low input to asynchronously initialize (or reset) the boundary scan
circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pull-
down resistor could be included to ensure the TAP is held in reset mode. The resistor values must be
chosen from
and must satisfy the parallel resistance value requirement. The values in
correspond to the resistor recommended when a single device is used and to the equivalent
parallel resistor when multiple devices are connected via a JTAG chain.
In critical applications, an upset in the JTAG circuit could allow entering an undesired JTAG state. In such
cases, Microsemi recommends tying off TRST to GND through a resistor placed close to the FPGA pin.
Note that to operate at all VJTAG voltages, 500
Ω
to 1 kΩ will satisfy the requirements.
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R e visio n 2
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 U1AFS600-2FG484YC
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FPGA | MICROSEMI | Preview |
