U1AFS600-2FG484
| Model | U1AFS600-2FG484 |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Datasheet Information
Revision
Advance v0.9
(continued)
Changes
In the
"484-Pin FBGA" table,
the function changed from V
CC33ACAP
to V
CC33A
for the
following pins:
AFS600: AB18
AFS1500: AB18
In the
"676-Pin FBGA" table,
the function changed from V
CC33ACAP
to V
CC33A
for the
following pins:
AFS1500: AD20
Page
3-20
3-28
Advance v0.8
(June 2007)
Figure 2-16 • Fusion Clocking Options
and the
"RC Oscillator" section
were updated
2-20, 2-21
to change GND_OSC and VCC_OSC to GNDOSC and VCCOSC.
Figure 2-19 • Fusion CCC Options: Global Buffers with the PLL Macro
was updated
to change the positions of OADIVRST and OADIVHALF, and a note was added.
The
"Crystal Oscillator" section
was updated to include information about controlling
and enabling/disabling the crystal oscillator.
Table 2-11 · Electrical Characteristics of the Crystal Oscillator
was updated to
change the typical value of I
DYNXTAL
for 0.032–0.2 MHz to 0.19.
The
"1.5 V Voltage Regulator" section
was updated to add "or floating" in the
paragraph stating that an external pull-down is required on TRST to power down the
VR.
The
"1.5 V Voltage Regulator" section
was updated to include information on
powering down with the VR.
This sentence was updated in the
"No-Glitch MUX (NGMUX)" section
to delete GLA:
The GLMUXCFG[1:0] configuration bits determine the source of the CLK inputs (i.e.,
internal signal or GLC).
In
Table 2-13 • NGMUX Configuration and Selection Table,
10 and 11 were deleted.
The method to enable sleep mode was updated for bit 0 in
Table 2-16 • RTC
Control/Status Register.
S2 was changed to D2 in
Figure 2-39 • Read Waveform (Pipe Mode, 32-bit access)
for RD[31:0] was updated.
The definitions for bits 2 and 3 were updated in
Table 2-24 • Page Status Bit
Definition.
Figure 2-46 • FlashROM Timing Diagram
was updated.
Table 2-26 • FlashROM Access Time
is new.
Figure 2-55 • Write Access After Write onto Same Address, Figure 2-56 • Read
Access After Write onto Same Address,
and
Figure 2-57 • Write Access After Read
onto Same Address
are new.
Table 2-31 • RAM4K9
and
Table 2-32 • RAM512X18
were updated.
The VAREF and SAMPLE functions were updated in
Table 2-36 • Analog Block Pin
Description.
The title of
Figure 2-72 • Timing Diagram for Current Monitor Strobe
was updated to
add the word "positive."
The
"Gate Driver" section
was updated to give information about the switching rate
in High Current Drive mode.
2-32
2-38
2-51
2-52
2-58
2-58
2-68–
2-70
2-71, 2-72
2-82
2-91
2-94
2-25
2-22
2-24
2-41
2-41
2-32
5- 10
R e visio n 2
Related PDFs
| Model | Description | Manufacturer | Operation |
|---|---|---|---|
 U1AFS600-2FG484YC
|
FPGA | MICROSEMI | Preview |
