U1AFS600-2FG484
| Model | U1AFS600-2FG484 |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
Table 3-12 •
Summary of I/O Input Buffer Power (per pin)—Default I/O Software Settings (continued)
VCCI (V)
Applicable to Advanced I/O Banks
Single-Ended
3.3 V LVTTL/LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
3.3 V PCI
3.3 V PCI-X
Differential
LVDS
LVPECL
Applicable to Standard I/O Banks
3.3 V LVTTL/LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
Notes:
1. PDC7 is the static power (where applicable) measured on VCCI.
2. PAC9 is the total dynamic power measured on VCC and VCCI.
Static Power
PDC7 (mW)
1
Dynamic Power
PAC9 (µW/MHz)
2
3.3
2.5
1.8
1.5
3.3
3.3
–
–
–
–
–
–
16.69
5.12
2.13
1.45
18.11
18.11
2.5
3.3
2.26
5.72
1.20
1.87
3.3
2.5
1.8
1.5
–
–
–
–
16.79
5.19
2.18
1.52
Revision 2
3- 19
Related PDFs
| Model | Description | Manufacturer | Operation |
|---|---|---|---|
 U1AFS600-2FG484YC
|
FPGA | MICROSEMI | Preview |
