U1AFS600-2FG484
| Model | U1AFS600-2FG484 |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Device Architecture
Summary of I/O Timing Characteristics – Default I/O Software Settings
Table 2-90 •
Summary of AC Measuring Points
Applicable to All I/O Bank Types
Standard
3.3 V LVTTL / 3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
3.3 V PCI-X
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
HSTL (II)
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
LVDS
LVPECL
Table 2-91 •
I/O AC Parameter Definitions
Parameter
t
DP
t
PY
t
DOUT
t
EOUT
t
DIN
t
PYS
t
HZ
t
ZH
t
LZ
t
ZL
t
ZHS
t
ZLS
Data to Pad delay through the Output Buffer
Pad to Data delay through the Input Buffer with Schmitt trigger disabled
Data to Output Buffer delay through the I/O interface
Enable to Output Buffer Tristate Control delay through the I/O interface
Input Buffer to Data delay through the I/O interface
Pad to Data delay through the Input Buffer with Schmitt trigger enabled
Enable to Pad delay through the Output Buffer—High to Z
Enable to Pad delay through the Output Buffer—Z to High
Enable to Pad delay through the Output Buffer—Low to Z
Enable to Pad delay through the Output Buffer—Z to Low
Enable to Pad delay through the Output Buffer with delayed enable—Z to High
Enable to Pad delay through the Output Buffer with delayed enable—Z to Low
Definition
Input Reference Voltage
(VREF_TYP)
–
–
–
–
–
–
0.8 V
0.8 V
1.0 V
1.0 V
0.75 V
0.75 V
1.25 V
1.25 V
1.5 V
1.5 V
–
–
Board Termination Voltage
(VTT_REF)
–
–
–
–
–
–
1.2 V
1.2 V
1.5 V
1.5 V
0.75 V
0.75 V
1.25 V
1.25 V
1.485 V
1.485 V
–
–
Measuring Trip Point
(Vtrip)
1.4 V
1.2 V
0.90 V
0.75 V
0.285 * VCCI (RR)
0.615 * VCCI (FF))
0.285 * VCCI (RR)
0.615 * VCCI (FF)
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
Cross point
Cross point
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R e visio n 2
Related PDFs
| Model | Description | Manufacturer | Operation |
|---|---|---|---|
 U1AFS600-2FG484YC
|
FPGA | MICROSEMI | Preview |
