U1AFS600-2FG484
| Model | U1AFS600-2FG484 |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Device Architecture
Analog Block
With the Fusion family, Microsemi has introduced the world's first mixed-mode FPGA solution.
Supporting a robust analog peripheral mix, Fusion devices will support a wide variety of applications. It is
this Analog Block that separates Fusion from all other FPGA solutions on the market today.
By combining both flash and high-speed CMOS processes in a single chip, these devices offer the best
of both worlds. The high-performance CMOS is used for building RAM resources. These high-
performance structures support device operation up to 350 MHz. Additionally, the advanced Microsemi
0.13 µm flash process incorporates high-voltage transistors and a high-isolation, triple-well process. Both
of these are suited for the flash-based programmable logic and nonvolatile memory structures.
High-voltage transistors support the integration of analog technology in several ways. They aid in noise
immunity so that the analog portions of the chip can be better isolated from the digital portions,
increasing analog accuracy. Because they support high voltages, Microsemi flash FPGAs can be
connected directly to high-voltage input signals, eliminating the need for external resistor divider
networks, reducing component count, and increasing accuracy. By supporting higher internal voltages,
the Microsemi advanced flash process enables high dynamic range on analog circuitry, increasing
precision and signal–noise ratio. Microsemi flash FPGAs also drive high-voltage outputs, eliminating the
need for external level shifters and drivers.
The unique triple-well process enables the integration of high-performance analog features with
increased noise immunity and better isolation. By increasing the efficiency of analog design, the triple-
well process also enables a smaller overall design size, reducing die size and cost.
The Analog Block consists of the Analog Quad I/O structure, RTC (for details refer to the
ADC, and ACM. All of these elements are combined in the
single Analog Block macro, with which the user implements this functionality (Figure
The Analog Block needs to be reset/reinitialized after the core powers up or the device is programmed.
An external reset/initialize signal, which can come from the internal voltage regulator when it powers up,
must be applied.
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Related PDFs
| Model | Description | Manufacturer | Operation |
|---|---|---|---|
 U1AFS600-2FG484YC
|
FPGA | MICROSEMI | Preview |
