U1AFS600-2FG484
| Model | U1AFS600-2FG484 |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
VersaNet Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are dependent upon I/O standard, and the clock may be
driven and conditioned internally by the CCC module.
and
present minimum and maximum global clock delays within the device Minimum and maximum
delays are measured with minimum and maximum loading, respectively.
Timing Characteristics
Table 2-5 •
AFS1500 Global Resource Timing
Commercial Temperature Range Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V
–2
Parameter
t
RCKL
t
RCKH
t
RCKMPWH
t
RCKMPWL
t
RCKSW
F
RMAX
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element located in a
fully loaded row (all available flip-flops are connected to the global net in the row).
3. For the derating values at specific junction temperature and voltage supply levels, refer to
–1
Min.
1
1.74
1.75
1.75
1.79
1.99
2.04
2.05
2.05
Std.
Max.
2
2.34
2.40
Units
ns
ns
ns
ns
Description
Input Low Delay for Global Clock
Input High Delay for Global Clock
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
Min.
1
1.53
1.53
Max.
2
Max.
2
Min.
1
0.26
0.29
0.34
ns
MHz
Table 2-6 •
AFS600 Global Resource Timing
Commercial Temperature Range Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V
–2
Parameter
t
RCKL
t
RCKH
t
RCKMPWH
t
RCKMPWL
t
RCKSW
F
RMAX
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element located in a
fully loaded row (all available flip-flops are connected to the global net in the row).
3. For the derating values at specific junction temperature and voltage supply levels, refer to
–1
1.49
1.54
1.44
1.44
1.70
1.75
Std.
Units
ns
ns
ns
ns
1.69
1.69
2.00
2.06
Description
Input Low Delay for Global Clock
Input High Delay for Global Clock
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
Min.
1
1.27
1.26
Max.
2
Min.
1
Max.
2
Min.
1
Max.
2
0.27
0.31
0.36
ns
MHz
Revision 2
2- 17
Related PDFs
| Model | Description | Manufacturer | Operation |
|---|---|---|---|
 U1AFS600-2FG484YC
|
FPGA | MICROSEMI | Preview |
