U1AFS600-2FG484
| Model | U1AFS600-2FG484 |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Device Architecture
I/O Register Specifications
Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
INBUF
Preset
X
D
Data_out
Y
F
X
G
X
X
L
Pad Out
DOUT
PRE
X D
Q
C DFN1E1P1
E
E
X
Core
Array
PRE
D
Q
DFN1E1P1
E
EOUT
H
X
A
X
X
X
Data Input I/O Register with:
Active High Enable
Active High Preset
Positive Edge Triggered
X
K
I
J
PRE
D
Q
DFN1E1P1
E
X
TRIBUF
INBUF
Data
Enable
X
B
X
INBUF
CLKBUF
CLK
CLKBUF
INBUF
INBUF
Data Output Register and
Enable Output Register with:
Active High Enable
Active High Preset
Postive Edge Triggered
CLK
Figure 2-135 •
Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
2- 21 4
R e visio n 2
D_Enable
Enable
Related PDFs
| Model | Description | Manufacturer | Operation |
|---|---|---|---|
 U1AFS600-2FG484YC
|
FPGA | MICROSEMI | Preview |
