U1AFS600-2FG484
| Model | U1AFS600-2FG484 |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
P
S-CELL
= N
S-CELL
* (PAC5 + (
α
1
/ 2) * PAC6) * F
CLK
N
S-CELL
is the number of VersaTiles used as sequential modules in the design. When a multi-tile
sequential cell is used, it should be accounted for as 1.
α
1
is the toggle rate of VersaTile outputs—guidelines are provided in
F
CLK
is the global clock signal frequency.
Standby Mode and Sleep Mode
P
S-CELL
= 0 W
Combinatorial Cells Dynamic Contribution—P
C-CELL
Operating Mode
P
C-CELL
= N
C-CELL
* (
α
1
/ 2) * PAC7 * F
CLK
N
C-CELL
is the number of VersaTiles used as combinatorial modules in the design.
α
1
is the toggle rate of VersaTile outputs—guidelines are provided in
F
CLK
is the global clock signal frequency.
Standby Mode and Sleep Mode
P
C-CELL
= 0 W
Routing Net Dynamic Contribution—P
NET
Operating Mode
P
NET
= (N
S-CELL
+ N
C-CELL
) * (
α
1
/ 2) * PAC8 * F
CLK
N
S-CELL
is the number VersaTiles used as sequential modules in the design.
N
C-CELL
is the number of VersaTiles used as combinatorial modules in the design.
α
1
is the toggle rate of VersaTile outputs—guidelines are provided in
F
CLK
is the global clock signal frequency.
Standby Mode and Sleep Mode
P
NET
= 0 W
I/O Input Buffer Dynamic Contribution—P
INPUTS
Operating Mode
P
INPUTS
= N
INPUTS
* (
α
2
/ 2) * PAC9 * F
CLK
N
INPUTS
is the number of I/O input buffers used in the design.
F
CLK
is the global clock signal frequency.
Standby Mode and Sleep Mode
P
INPUTS
= 0 W
α
2
is the I/O buffer toggle rate—guidelines are provided in
I/O Output Buffer Dynamic Contribution—P
OUTPUTS
Operating Mode
P
OUTPUTS
= N
OUTPUTS
* (
α
2
/ 2) *
β
1
* PAC10 * F
CLK
N
OUTPUTS
is the number of I/O output buffers used in the design.
α
2
is the I/O buffer toggle rate—guidelines are provided in
β
1
is the I/O buffer enable rate—guidelines are provided in
F
CLK
is the global clock signal frequency.
Standby Mode and Sleep Mode
P
OUTPUTS
= 0 W
Revision 2
3- 25
Related PDFs
| Model | Description | Manufacturer | Operation |
|---|---|---|---|
 U1AFS600-2FG484YC
|
FPGA | MICROSEMI | Preview |
