U1AFS600-2FG484
| Model | U1AFS600-2FG484 |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
connected between the VAREF and ADCGNDREF pins. The VAREFSEL control pin is used to select the
reference voltage.
Table 2-42 •
VAREF Bit Function
Name
VAREF
Bit
0
Reference voltage selection
0 – Internal voltage reference selected. VAREF pin outputs 2.56 V.
1 – Input external voltage reference from VAREF and ADCGNDREF
Function
ADC Clock
The speed of the ADC depends on its internal clock, ADCCLK, which is not accessible to users. The
ADCCLK is derived from SYSCLK. Input signal TVC[7:0], Time Divider Control, determines the speed of
the ADCCLK in relationship to SYSCLK, based on
t
ADCCLK
=
4
× (
1
+
TVC
) ×
t
SYSCLK
EQ 15
TVC: Time Divider Control (0–255)
t
ADCCLK
is the period of ADCCLK, and must be between 0.5 MHz and 10 MHz
t
SYSCLK
is the period of SYSCLK
Table 2-43 •
TVC Bits Function
Name
TVC
Bits
[7:0]
Function
SYSCLK divider control
The frequency of ADCCLK, f
ADCCLK
, must be within 0.5 Hz to 10 MHz.
The inputs to the ADC are synchronized to SYSCLK. A conversion is initiated by asserting the
ADCSTART signal on a rising edge of SYSCLK.
and
show the timing diagram for the ADC.
Acquisition Time or Sample Time Control
Acquisition time (t
SAMPLE
) specifies how long an analog input signal has to charge the internal capacitor
array.
shows a simplified internal input sampling mechanism of a SAR ADC.
Sample and Hold
R
source
Z
INAD
C
INAD
Figure 2-86 •
Simplified Sample and Hold Circuitry
The internal impedance (Z
INAD
), external source resistance (R
SOURCE
), and sample capacitor (C
INAD
)
form a simple RC network. As a result, the accuracy of the ADC can be affected if the ADC is given
insufficient time to charge the capacitor. To resolve this problem, you can either reduce the source
resistance or increase the sampling time by changing the acquisition time using the STC signal.
through
can be used to calculate the acquisition time required for a given input. The STC
signal gives the number of sample periods in ADCCLK for the acquisition time of the desired signal. If the
actual acquisition time is higher than the STC value, the settling time error can affect the accuracy of the
ADC, because the sampling capacitor is only partially charged within the given sampling cycle. Example
acquisition times are given in
and
When controlling the sample time for the ADC
Revision 2
2- 109
Related PDFs
| Model | Description | Manufacturer | Operation |
|---|---|---|---|
 U1AFS600-2FG484YC
|
FPGA | MICROSEMI | Preview |
