U1AFS600-2FG484
| Model | U1AFS600-2FG484 |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Fusion Family of Mixed Signal FPGAs
Temporary overshoots are allowed according to
Solution 1
Fusion I/O Input
Off-Chip
5.5 V
On-Chip
3.3 V
Rext1
Rext2
Requires two board resistors,
LVCMOS 3.3 V I/Os
Figure 2-101 •
Solution 1
Solution 2
The board-level design must ensure that the reflected waveform at the pad does not exceed limits
provided in
This is a long-term reliability requirement.
This scheme will also work for a 3.3 V PCI/PCI-X configuration, but the internal diode should not be used
for clamping, and the voltage must be limited by the external resistors and Zener, as shown in
Relying on the diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V.
Solution 2
Fusion I/O Input
Off-Chip
5.5 V
On-Chip
3.3 V
Rext1
Zener
3.3 V
Requires one board resistor, one
Zener 3.3 V diode, LVCMOS 3.3 V I/Os
Figure 2-102 •
Solution 2
Revision 2
2- 147
Related PDFs
| Model | Description | Manufacturer | Operation |
|---|---|---|---|
 U1AFS600-2FG484YC
|
FPGA | MICROSEMI | Preview |
