U1AFS600-2FG484
| Model | U1AFS600-2FG484 |
| Description | Field Programmable Gate Array, |
| PDF file | Total 334 pages (File size: 18M) |
| Chip Manufacturer | MICROSEMI |
Device Architecture
Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
Pad Out
DOUT
Data
D
CC
Q
EE
Y
Core
Array
Data_out FF
TRIBUF
INBUF
INBUF
D
Q
DFN1E1C1
E
DFN1E1C1
GG
E
EOUT
CLR
Enable
BB
CLR
LL
HH
CLKBUF
CLK
AA
JJ
DD
KK
Data Input I/O Register with
Active High Enable
Active High Clear
Positive Edge Triggered
INBUF
CLR
D
Q
DFN1E1C1
E
CLR
Data Output Register and
Enable Output Register with
Active High Enable
Active High Clear
Positive Edge Triggered
INBUF
INBUF
CLKBUF
Figure 2-136 •
Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
2- 21 6
R e visio n 2
D_Enable
Enable
CLK
Related PDFs
| Model | Description | Manufacturer | Operation |
|---|---|---|---|
 U1AFS600-2FG484YC
|
FPGA | MICROSEMI | Preview |
