MC9S12XDP512CFU
Model | MC9S12XDP512CFU |
Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
PDF file | Total 1348 pages (File size: 8M) |
Chip Manufacturer | PHILIPS |
Table 24-60. Register Availability per Port
1
Port
J
AD1
Data
yes
yes
Data
Direction
yes
yes
Input
yes
—
Reduced
Drive
yes
yes
Pull
Enable
yes
yes
Polarity
Select
yes
—
Wired-OR
Mode
—
—
Interrupt
Enable
yes
—
Interrupt
Flag
yes
—
1. Each cell represents one register with individual configuration bits
24.0.6
24.0.6.1
Registers
Data Register
This register holds the value driven out to the pin if the pin is used as a general purpose I/O.
Writing to this register has only an effect on the pin if the pin is used as general purpose output.
When reading this address, the buffered state of the pin is returned if the associated data direction
register bit is set to “0”.
If the data direction register bits are set to logic level “1”, the contents of the data register is
returned. This is independent of any other configuration (Figure
24-68).
24.0.6.2
Input Register
This is a read-only register and always returns the buffered state of the pin (Figure
24-68).
24.0.6.3
Data Direction Register
This register defines whether the pin is used as an input or an output.
If a peripheral module controls the pin the contents of the data direction register is ignored
(Figure
24-68).
PTI
0
1
PT
0
1
PIN
DDR
data out
0
1
Module
output enable
module enable
Figure 24-68. Illustration of I/O Pin Functionality