MC9S12XDP512CFU
| Model | MC9S12XDP512CFU |
| Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
| PDF file | Total 1348 pages (File size: 8M) |
| Chip Manufacturer | PHILIPS |
Chapter 19 S12X Debug (S12XDBGV2) Module
19.3.1.6
0x0026
Debug Count Register (DBGCNT)
7
6
5
4
3
2
1
0
R
W
Reset
POR
0
0
0
—
0
—
0
—
0
CNT
—
0
—
0
—
0
—
0
Unimplemented or Reserved
Figure 19-9. Debug Count Register (DBGCNT)
Read: Anytime
Write: Never
Table 19-17. DBGCNT Field Descriptions
Field
6–0
CNT[6:0]
Description
Count Value
— The CNT bits [6:0] indicate the number of valid data 64-bit data lines stored in the trace buffer.
Table 19-18
shows the correlation between the CNT bits and the number of valid data lines in the trace buffer.
When the CNT rolls over to 0, the TBF bit in DBGSR is set and incrementing of CNT will continue in end-trigger
or mid-trigger mode. The DBGCNT register is cleared when ARM in DBGC1 is written to a 1. The DBGCNT
register is cleared by power-on-reset initialization but is not cleared by other system resets. Thus should a reset
occur during a debug session, the DBGCNT register still indicates after the reset, the number of valid trace buffer
entries stored before the reset occurred. The DBGCNT register is not decremented when reading from the trace
buffer.
Table 19-18. CNT Decoding Table
TBF (DBGSR)
0
0
0
0
CNT[6:0]
0000000
0000001
0000010
0000011
0000100
0000110
..
1111100
1111110
0000000
0000010
..
..
1111110
Description
No data valid
32 bits of one line valid
1
1 line valid
1.5 lines valid
1
2 lines valid
3 lines valid
..
62 lines valid
63 lines valid
64 lines valid; if using begin-trigger alignment,
ARM bit will be cleared and the tracing session ends.
64 lines valid,
oldest data has been overwritten by most recent data
0
1
1
1
This applies to normal/loop1 modes when tracing from either CPU or XGATE only.
MC9S12XDP512 Data Sheet, Rev. 2.21
704
Freescale Semiconductor
