MC9S12XDP512CFU
| Model | MC9S12XDP512CFU |
| Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
| PDF file | Total 1348 pages (File size: 8M) |
| Chip Manufacturer | PHILIPS |
Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)
5.3.2.11
R
W
Reset
ATD Input Enable Register (ATDDIEN)
7
6
5
4
3
2
1
0
IEN7
0
IEN6
0
IEN5
0
IEN4
0
IEN3
0
IEN2
0
IEN1
0
IEN0
0
Figure 5-13. ATD Input Enable Register (ATDDIEN)
Read: Anytime
Write: Anytime
Table 5-21. ATDDIEN Field Descriptions
Field
7–0
IEN[7:0]
Description
ATD Digital Input Enable on channel x (x = 7, 6, 5, 4, 3, 2, 1, 0)
— This bit controls the digital input buffer from
the analog input pin (ANx) to PTADx data register.
0 Disable digital input buffer to PTADx
1 Enable digital input buffer to PTADx.
Note:
Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while
simultaneously using it as an analog port, there is potentially increased power consumption because the
digital input buffer maybe in the linear region.
5.3.2.12
Port Data Register (PORTAD)
The data port associated with the ATD can be configured as general-purpose I/O or input only, as specified
in the device overview. The port pins are shared with the analog A/D inputs AN7–0.
7
6
5
4
3
2
1
0
R
W
Reset
Pin
Function
PTAD7
1
AN7
PTAD6
1
AN6
PTAD5
1
AN5
PTAD4
1
AN4
PTAD3
1
AN3
PTAD2
1
AN2
PTAD1
1
AN1
PTAD0
1
AN0
= Unimplemented or Reserved
Figure 5-14. Port Data Register (PORTAD)
Read: Anytime
Write: Anytime, no effect
The A/D input channels may be used for general purpose digital input.
Table 5-22. PORTAD Field Descriptions
Field
7–0
PTAD[7:0]
Description
A/D Channel x (ANx) Digital Input (x = 7, 6, 5, 4, 3, 2, 1, 0)
— If the digital input buffer on the ANx pin is enabled
(IENx = 1) or channel x is enabled as external trigger (ETRIGE = 1,ETRIGCH[2–0] = x,ETRIGSEL = 0) read
returns the logic level on ANx pin (signal potentials not meeting V
IL
or V
IH
specifications will have an
indeterminate value).
If the digital input buffers are disabled (IENx = 0) and channel x is not enabled as external trigger, read returns
a “1”.
Reset sets all PORTAD0 bits to “1”.
MC9S12XDP512 Data Sheet, Rev. 2.21
178
Freescale Semiconductor
