MC9S12XDP512CFU
| Model | MC9S12XDP512CFU |
| Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
| PDF file | Total 1348 pages (File size: 8M) |
| Chip Manufacturer | PHILIPS |
Chapter 9 Inter-Integrated Circuit (IICV2) Block Description
9.4
Functional Description
This section provides a complete functional description of the IICV2.
9.4.1
I-Bus Protocol
The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices
connected to it must have open drain or open collector outputs. Logic AND function is exercised on both
lines with external pull-up resistors. The value of these resistors is system dependent.
Normally, a standard communication is composed of four parts: START signal, slave address transmission,
data transfer and STOP signal. They are described briefly in the following sections and illustrated in
Figure 9-9.
MSB
SCL
1
2
3
4
5
6
7
LSB
8
9
MSB
1
2
3
4
5
6
7
LSB
8
9
SDA
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
XXX
D7
D6
D5
D4
D3
D2
D1
D0
Start
Signal
Calling Address
Read/
Write
Ack
Bit
Data Byte
No Stop
Ack Signal
Bit
LSB
MSB
SCL
1
2
3
4
5
6
7
LSB
8
9
MSB
1
2
3
4
5
6
7
8
9
SDA
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
XX
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
Start
Signal
Calling Address
Read/
Write
Ack
Bit
Repeated
Start
Signal
New Calling Address
Read/
Write
No Stop
Ack Signal
Bit
Figure 9-9. IIC-Bus Transmission Signals
9.4.1.1
START Signal
When the bus is free, i.e. no master device is engaging the bus (both SCL and SDA lines are at logical
high), a master may initiate communication by sending a START signal.As shown in
Figure 9-9,
a START
signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning
of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of
their idle states.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
409
