MC9S12XDP512CFU
| Model | MC9S12XDP512CFU |
| Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
| PDF file | Total 1348 pages (File size: 8M) |
| Chip Manufacturer | PHILIPS |
Chapter 2 Clocks and Reset Generator (S12CRGV6)
2.5
Resets
This section describes how to reset the CRG, and how the CRG itself controls the reset of the MCU. It
explains all special reset requirements. Since the reset generator for the MCU is part of the CRG, this
section also describes all automatic actions that occur during or as a result of individual reset conditions.
The reset values of registers and signals are provided in
Section 2.3, “Memory Map and Register
Definition”.
All reset sources are listed in
Table 2-14.
Refer to MCU specification for related vector
addresses and priorities.
Table 2-14. Reset Summary
Reset Source
Power on Reset
Low Voltage Reset
External Reset
Illegal Address Reset
Clock Monitor Reset
COP Watchdog Reset
Local Enable
None
None
None
None
PLLCTL (CME = 1, SCME = 0)
COPCTL (CR[2:0] nonzero)
2.5.1
Description of Reset Operation
The reset sequence is initiated by any of the following events:
• Low level is detected at the RESET pin (external reset)
• Power on is detected
• Low voltage is detected
• Illegal Address Reset is detected (see S12XMMC Block Guide for details)
• COP watchdog times out
• Clock monitor failure is detected and self-clock mode was disabled (SCME=0)
Upon detection of any reset event, an internal circuit drives the RESET pin low for 128 SYSCLK cycles
(see
Figure 2-25).
Since entry into reset is asynchronous, it does not require a running SYSCLK. However,
the internal reset circuit of the CRG cannot sequence out of current reset condition without a running
SYSCLK. The number of 128 SYSCLK cycles might be increased by n = 3 to 6 additional SYSCLK cycles
depending on the internal synchronization latency. After 128 + n SYSCLK cycles the RESET pin is
released. The reset generator of the CRG waits for additional 64 SYSCLK cycles and then samples the
RESET pin to determine the originating source.
Table 2-15
shows which vector will be fetched.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
113
