MC9S12XDP512CFU
Model | MC9S12XDP512CFU |
Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
PDF file | Total 1348 pages (File size: 8M) |
Chip Manufacturer | PHILIPS |
Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1)
7
6
5
4
3
2
1
0
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 25-6. RESERVED2
All bits read 0 and are not writable.
25.3.2.4
EEPROM Configuration Register (ECNFG)
The ECNFG register enables the EEPROM interrupts.
7
6
5
4
3
2
1
0
R
CBEIE
W
Reset
0
0
CCIE
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 25-7. EEPROM Configuration Register (ECNFG)
CBEIE and CCIE bits are readable and writable while all remaining bits read 0 and are not writable.
Table 25-3. ECNFG Field Descriptions
Field
7
CBEIE
Description
Command Buffer Empty Interrupt Enable
— The CBEIE bit enables an interrupt in case of an empty command
buffer in the EEPROM module.
0 Command Buffer Empty interrupt disabled.
1 An interrupt will be requested whenever the CBEIF flag (see
Section 25.3.2.6, “EEPROM Status Register
(ESTAT)”)
is set.
Command Complete Interrupt Enable
— The CCIE bit enables an interrupt in case all commands have been
0 Command Complete interrupt disabled.
1 An interrupt will be requested whenever the CCIF flag (see
Section 25.3.2.6, “EEPROM Status Register
(ESTAT)”)
is set.
6
CCIE
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
1045