MC9S12XDP512CFU
Model | MC9S12XDP512CFU |
Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
PDF file | Total 1348 pages (File size: 8M) |
Chip Manufacturer | PHILIPS |
Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
uncertain
t
pign
t
pval
Figure 24-69. Interrupt Glitch Filter on Port P, H, and J (PPS = 0)
Table 24-62. Pulse Detection Criteria
Mode
Pulse
STOP
Ignored
Uncertain
Valid
t
pulse
≤
3
3 < t
pulse
< 4
t
pulse
≥
4
Unit
Bus clocks
Bus clocks
Bus clocks
STOP
1
t
pulse
≤
t
pign
t
pign
< t
pulse
< t
pval
t
pulse
≥
t
pval
1. These values include the spread of the oscillator frequency over
temperature, voltage and process.
t
pulse
Figure 24-70. Pulse Illustration
A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by
4 consecutive samples of an active level directly or indirectly.
The filters are continuously clocked by the bus clock in run and wait mode. In stop mode, the clock is
generated by an RC-oscillator in the port integration module. To maximize current saving the RC
oscillator runs only if the following condition is true on any pin individually:
Sample count <= 4 and interrupt enabled (PIE = 1) and interrupt flag not set (PIF = 0).
24.0.9
24.0.9.1
Low-Power Options
Run Mode
No low-power options exist for this module in run mode.
MC9S12XDP512 Data Sheet, Rev. 2.21
1034
Freescale Semiconductor