MC9S12XDP512CFU
| Model | MC9S12XDP512CFU |
| Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
| PDF file | Total 1348 pages (File size: 8M) |
| Chip Manufacturer | PHILIPS |
Chapter 16 Interrupt (S12XINTV1)
16.1.1
Glossary
The following terms and abbreviations are used in the document.
Table 16-1. Terminology
Term
CCR
DMA
INT
IPL
ISR
MCU
XGATE
IRQ
XIRQ
Meaning
Condition Code Register (in the S12X CPU)
Direct Memory Access
Interrupt
Interrupt Processing Level
Interrupt Service Routine
Micro-Controller Unit
please refer to the "XGATE Block Guide"
refers to the interrupt request associated with the IRQ pin
refers to the interrupt request associated with the XIRQ pin
16.1.2
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Features
Interrupt vector base register (IVBR)
One spurious interrupt vector (at address vector base
1
+ 0x0010).
2–113 I bit maskable interrupt vector requests (at addresses vector base + 0x0012–0x00F2).
Each I bit maskable interrupt request has a configurable priority level and can be configured to be
handled by either the CPU or the XGATE module
2
.
I bit maskable interrupts can be nested, depending on their priority levels.
One X bit maskable interrupt vector request (at address vector base + 0x00F4).
One non-maskable software interrupt request (SWI) or background debug mode vector request (at
address vector base + 0x00F6).
One non-maskable unimplemented opcode trap (TRAP) vector (at address vector base + 0x00F8).
Three system reset vectors (at addresses 0xFFFA–0xFFFE).
Determines the highest priority DMA and interrupt vector requests, drives the vector to the XGATE
module or to the bus on CPU request, respectively.
Wakes up the system from stop or wait mode when an appropriate interrupt request occurs or
whenever XIRQ is asserted, even if X interrupt is masked.
XGATE can wake up and execute code, even with the CPU remaining in stop or wait mode.
16.1.3
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Modes of Operation
Run mode
This is the basic mode of operation.
1. The vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used
as upper byte) and 0x00 (used as lower byte).
2. The IRQ interrupt can only be handled by the CPU
MC9S12XDP512 Data Sheet, Rev. 2.21
596
Freescale Semiconductor
