MC9S12XDP512CFU
| Model | MC9S12XDP512CFU |
| Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
| PDF file | Total 1348 pages (File size: 8M) |
| Chip Manufacturer | PHILIPS |
Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1)
7
6
5
4
3
2
1
0
R
W
Reset
0
MRDS
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 28-6. Flash Test Mode Register (FTSTMOD —Normal Mode)
7
6
5
4
3
2
1
0
R
W
Reset
0
MRDS
0
0
0
WRALL
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 28-7. Flash Test Mode Register (FTSTMOD — Special Mode)
MRDS bits are readable and writable while all remaining bits read 0 and are not writable in normal mode.
The WRALL bit is writable only in special mode to simplify mass erase and erase verify operations. When
writing to the FTSTMOD register in special mode, all unimplemented/reserved bits must be written to 0.
Table 28-6. FTSTMOD Field Descriptions
Field
6:5
MRDS[1:0]
4
WRALL
Description
Margin Read Setting
— The MRDS[1:0] bits are used to set the sense-amp margin level for reads of the Flash
array as shown in
Table 28-7.
Write to all Register Banks
— If the WRALL bit is set, all banked FDATA registers sharing the same register
address will be written simultaneously during a register write.
0 Write only to the FDATA register bank selected using BKSEL.
1 Write to all FDATA register banks.
Table 28-7. FTSTMOD Margin Read Settings
MRDS[1:0]
00
01
10
11
Margin Read Setting
Normal
Program Margin
1
Erase Margin
2
Normal
1 Flash array reads will be sensitive to program margin.
2 Flash array reads will be sensitive to erase margin.
28.3.2.4
Flash Configuration Register (FCNFG)
The FCNFG register enables the Flash interrupts and gates the security backdoor writes.
MC9S12XDP512 Data Sheet, Rev. 2.21
1156
Freescale Semiconductor
