MC9S12XDP512CFU
| Model | MC9S12XDP512CFU |
| Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
| PDF file | Total 1348 pages (File size: 8M) |
| Chip Manufacturer | PHILIPS |
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1)
29.6.2
Unsecuring the MCU in Special Single Chip Mode using BDM
The MCU can be unsecured in special single chip mode by erasing the Flash module by the following
method:
• Reset the MCU into special single chip mode, delay while the erase test is performed by the BDM
secure ROM, send BDM commands to disable protection in the Flash module, and execute a mass
erase command write sequence to erase the Flash memory.
After the CCIF flag sets to indicate that the mass operation has completed, reset the MCU into special
single chip mode. The BDM secure ROM will verify that the Flash memory is erased and will assert the
UNSEC bit in the BDM status register. This BDM action will cause the MCU to override the Flash security
state and the MCU will be unsecured. All BDM commands will be enabled and the Flash security byte
may be programmed to the unsecure state by the following method:
• Send BDM commands to execute a word program sequence to program the Flash security byte to
the unsecured state and reset the MCU.
29.7
29.7.1
Resets
Flash Reset Sequence
On each reset, the Flash module executes a reset sequence to hold CPU activity while loading the following
registers from the Flash memory according to
Table 29-1:
• FPROT — Flash Protection Register (see
• FCTL - Flash Control Register (see
Section 29.3.2.8).
• FSEC — Flash Security Register (see
Section 29.3.2.2).
29.7.2
Reset While Flash Command Active
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
29.8
Interrupts
The Flash module can generate an interrupt when all Flash command operations have completed, when the
Flash address, data and command buffers are empty.
Table 29-19. Flash Interrupt Sources
Interrupt Source
Flash Address, Data and Command Buffers empty
All Flash commands completed
Interrupt Flag
CBEIF
(FSTAT register)
CCIF
(FSTAT register)
Local Enable
CBEIE
(FCNFG register)
CCIE
(FCNFG register)
Global (CCR) Mask
I Bit
I Bit
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
1229
