MC9S12XDP512CFU
Model | MC9S12XDP512CFU |
Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
PDF file | Total 1348 pages (File size: 8M) |
Chip Manufacturer | PHILIPS |
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
Table 23-42. PPSP Field Descriptions
Field
7–0
PPSP[7:0]
Description
Polarity Select Port P
0 Falling edge on the associated port P pin sets the associated flag bit in the PIFP register.A pull-up device is
connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is used
as input.
1 Rising edge on the associated port P pin sets the associated flag bit in the PIFP register.A pull-down device
is connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is
used as input.
23.0.5.44 Port P Interrupt Enable Register (PIEP)
7
6
5
4
3
2
1
0
R
PIEP7
W
Reset
0
0
0
0
0
0
0
0
PIEP6
PIEP5
PIEP4
PIEP3
PIEP2
PIEP1
PIEP0
Figure 23-46. Port P Interrupt Enable Register (PIEP)
Read: Anytime.
Write: Anytime.
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with
Port P.
Table 23-43. PIEP Field Descriptions
Field
7–0
PIEP[7:0]
Interrupt Enable Port P
0 Interrupt is disabled (interrupt flag masked).
1 Interrupt is enabled.
Description
23.0.5.45 Port P Interrupt Flag Register (PIFP)
7
6
5
4
3
2
1
0
R
PIFP7
W
Reset
0
0
0
0
0
0
0
0
PIFP6
PIFP5
PIFP4
PIFP3
PIFP2
PIFP1
PIFP0
Figure 23-47. Port P Interrupt Flag Register (PIFP)
Read: Anytime.
Write: Anytime.
MC9S12XDP512 Data Sheet, Rev. 2.21
946
Freescale Semiconductor