MC9S12XDP512CFU
Model | MC9S12XDP512CFU |
Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
PDF file | Total 1348 pages (File size: 8M) |
Chip Manufacturer | PHILIPS |
Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
“MSCAN Control Register 0 (CANCTL0)”).
In case of a transmission, the CPU can only read the time
stamp after the respective transmit buffer has been flagged empty.
The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer
overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The
CPU can only read the time stamp registers.
7
6
5
4
3
2
1
0
R
W
Reset:
TSR15
TSR14
TSR13
TSR12
TSR11
TSR10
TSR9
TSR8
x
x
x
x
x
x
x
x
Figure 10-37. Time Stamp Register — High Byte (TSRH)
7
6
5
4
3
2
1
0
R
W
Reset:
TSR7
TSR6
TSR5
TSR4
TSR3
TSR2
TSR1
TSR0
x
x
x
x
x
x
x
x
Figure 10-38. Time Stamp Register — Low Byte (TSRL)
Read: Anytime when TXEx flag is set (see
Section 10.3.2.7, “MSCAN Transmitter Flag Register
(CANTFLG)”)
and the corresponding transmit buffer is selected in CANTBSEL (see
Section 10.3.2.11,
“MSCAN Transmit Buffer Selection Register (CANTBSEL)”).
10.4
10.4.1
Functional Description
General
This section provides a complete functional description of the MSCAN. It describes each of the features
and modes listed in the introduction.
MC9S12XDP512 Data Sheet, Rev. 2.21
456
Freescale Semiconductor