MC9S12XDP512CFU
| Model | MC9S12XDP512CFU |
| Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
| PDF file | Total 1348 pages (File size: 8M) |
| Chip Manufacturer | PHILIPS |
Chapter 21 External Bus Interface (S12XEBIV2)
21.3.2.2
R
W
Reset
External Bus Interface Control Register 1 (EBICTL1)
7
6
5
4
3
2
1
0
EWAITE
0
0
0
0
0
0
0
0
0
EXSTR2
1
EXSTR1
1
EXSTR0
1
= Unimplemented or Reserved
Figure 21-4. External Bus Interface Control Register 1 (EBICTL1)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data are read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
This register is used to configure the external access stretch (wait) function.
Table 21-5. EBICTL1 Field Descriptions
Field
7
EWAITE
Description
External Wait Enable
— This bit enables the external access stretch function using the external EWAIT input
pin. Enabling this feature may have effect on the minimum number of additional stretch cycles (refer to
Table 21-6).
External wait feature is only active if enabled in normal expanded mode and emulation expanded mode; function
0 External wait is disabled
1 External wait is enabled
External Access Stretch Bits 2, 1, 0
— This three bit field determines the amount of additional clock stretch
cycles on every access to the external address space as shown in
Table 21-6.
The minimum number of stretch
cycles depends on the EWAITE setting.
Stretch cycles are added as programmed in normal expanded mode and emulation expanded mode; function
not available in all other operating modes.
2–0
EXSTR[2:0]
Table 21-6. External Access Stretch Bit Definition
Number of Stretch Cycles
EXSTR[2:0]
EWAITE = 0
000
001
010
011
100
101
110
111
1 cycle
2 cycles
3 cycles
4 cycles
5 cycles
6 cycles
7 cycles
8 cycles
EWAITE = 1
>= 2 cycles
>= 2 cycles
>= 3 cycles
>= 4 cycles
>= 5 cycles
>= 6 cycles
>= 7 cycles
>= 8 cycles
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
793
