MC9S12XDP512CFU
Model | MC9S12XDP512CFU |
Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
PDF file | Total 1348 pages (File size: 8M) |
Chip Manufacturer | PHILIPS |
Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
Table 24-3. Pin Configuration Summary
DDR
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
IO
x
x
x
x
x
x
x
0
1
0
1
0
1
0
1
RDR
x
x
x
x
x
x
x
0
0
1
1
0
0
1
1
PE
0
1
1
0
0
1
1
x
x
x
x
x
x
x
x
PS
1
x
0
1
0
1
0
1
x
x
x
x
0
1
0
1
IE
2
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Input
Input
Input
Input
Input
Input
Input
Output, full drive to 0
Output, full drive to 1
Output, reduced drive to 0
Output, reduced drive to 1
Output, full drive to 0
Output, full drive to 1
Output, reduced drive to 0
Output, reduced drive to 1
Function
Pull Device
Disabled
Pull Up
Pull Down
Disabled
Disabled
Pull Up
Pull Down
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Interrupt
Disabled
Disabled
Disabled
Falling edge
Rising edge
Falling edge
Rising edge
Disabled
Disabled
Disabled
Disabled
Falling edge
Rising edge
Falling edge
Rising edge
1. Always “0” on Port A, B, C, D, E, K, AD0, and AD1.
2. Applicable only on Port P, H, and J.
NOTE
All register bits in this module are completely synchronous to internal
clocks during a register read.
Register
Name
PORTA
R
W
PORTB
R
W
DDRA
R
W
DDRB
R
W
Bit 7
PA7
6
PA6
5
PA5
4
PA4
3
PA3
2
PA2
1
PA1
Bit 0
PA0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
= Unimplemented or Reserved
Figure 24-2. PIM Register Summary (Sheet 1 of 7)
MC9S12XDP512 Data Sheet, Rev. 2.21
986
Freescale Semiconductor