MC9S12XDP512CFU
| Model | MC9S12XDP512CFU |
| Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
| PDF file | Total 1348 pages (File size: 8M) |
| Chip Manufacturer | PHILIPS |
Chapter 16 Interrupt (S12XINTV1)
16.3.1.4
Interrupt Request Configuration Data Registers (INT_CFDATA0–7)
The eight register window visible at addresses INT_CFDATA0–7 contains the configuration data for the
block of eight interrupt requests (out of 128) selected by the interrupt configuration address register
(INT_CFADDR) in ascending order. INT_CFDATA0 represents the interrupt configuration data register
of the vector with the lowest address in this block, while INT_CFDATA7 represents the interrupt
configuration data register of the vector with the highest address, respectively.
Address: 0x0128
7
6
5
4
3
2
1
0
R
W
Reset
RQST
0
0
0
0
0
0
0
0
0
0
PRIOLVL[2:0]
0
1
1
= Unimplemented or Reserved
Figure 16-6. Interrupt Request Configuration Data Register 0 (INT_CFDATA0)
1
Please refer to the notes following the PRIOLVL[2:0] description below.
Address: 0x0129
7
6
5
4
3
2
1
0
R
W
Reset
RQST
0
0
0
0
0
0
0
0
0
0
PRIOLVL[2:0]
0
1
1
= Unimplemented or Reserved
Figure 16-7. Interrupt Request Configuration Data Register 1 (INT_CFDATA1)
1
Please refer to the notes following the PRIOLVL[2:0] description below.
Address: 0x012A
7
6
5
4
3
2
1
0
R
W
Reset
RQST
0
0
0
0
0
0
0
0
0
0
PRIOLVL[2:0]
0
1
1
= Unimplemented or Reserved
Figure 16-8. Interrupt Request Configuration Data Register 2 (INT_CFDATA2)
1
Please refer to the notes following the PRIOLVL[2:0] description below.
Address: 0x012B
7
6
5
4
3
2
1
0
R
W
Reset
RQST
0
0
0
0
0
0
0
0
0
0
PRIOLVL[2:0]
0
1
1
= Unimplemented or Reserved
Figure 16-9. Interrupt Request Configuration Data Register 3 (INT_CFDATA3)
1
Please refer to the notes following the PRIOLVL[2:0] description below.
MC9S12XDP512 Data Sheet, Rev. 2.21
604
Freescale Semiconductor
