MC9S12XDP512CFU
Model | MC9S12XDP512CFU |
Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
PDF file | Total 1348 pages (File size: 8M) |
Chip Manufacturer | PHILIPS |
Chapter 14 Voltage Regulator (S12VREG3V3V5)
14.1.3
Block Diagram
Figure 14-1
shows the function principle of VREG_3V3 by means of a block diagram. The regulator core
REG consists of two parallel subblocks, REG1 and REG2, providing two independent output voltages.
REG2
V
DDR
REG
VBG
REG1
V
DDA
V
DDPLL
V
SSPLL
V
DD
LVD
LVR
LVR
POR
POR
V
SSA
V
SS
V
REGEN
CTRL
LVI
API
Rate
Select
API
API
Bus Clock
LVD: Low-Voltage Detect
LVR: Low-Voltage Reset
POR: Power-On Reset
REG: Regulator Core
CTRL: Regulator Control
API: Auto. Periodical Interrupt
PIN
Figure 14-1. VREG_3V3 Block Diagram
MC9S12XDP512 Data Sheet, Rev. 2.21
556
Freescale Semiconductor