MC9S12XDP512CFU
Model | MC9S12XDP512CFU |
Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
PDF file | Total 1348 pages (File size: 8M) |
Chip Manufacturer | PHILIPS |
Chapter 9 Inter-Integrated Circuit (IICV2) Block Description
Clear
IBIF
Y
Master
Mode
?
N
TX
Tx/Rx
?
RX
Y
Arbitration
Lost
?
N
Last Byte
Transmitted
?
N
Y
Clear IBAL
RXAK=0
?
Y
End Of
Addr Cycle
(Master Rx)
?
N
N
Last
Byte To Be Read
?
N
Y
N
IAAS=1
?
Y
Y
IAAS=1
?
N
Address Transfer
Y
Y
2nd Last
Byte To Be Read
?
N
Y
(Read)
SRW=1
?
N (Write)
Y
Data Transfer
TX/RX
?
TX
ACK From
Receiver
?
N
Read Data
From IBDR
And Store
RX
Write Next
Byte To IBDR
Set TXAK =1
Generate
Stop Signal
Set TX
Mode
Write Data
To IBDR
Tx Next
Byte
Switch To
Rx Mode
Set RX
Mode
Switch To
Rx Mode
Dummy Read
From IBDR
Generate
Stop Signal
Read Data
From IBDR
And Store
Dummy Read
From IBDR
Dummy Read
From IBDR
RTI
Figure 9-12. Flow-Chart of Typical IIC Interrupt Routine
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
417