MC9S12XDP512CFU
Model | MC9S12XDP512CFU |
Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
PDF file | Total 1348 pages (File size: 8M) |
Chip Manufacturer | PHILIPS |
Chapter 11 Serial Communication Interface (S12SCIV5)
11.4.6
Receiver
Internal Bus
SBR12:SBR0
SCI Data Register
11-Bit Receive Shift Register
8
7
6
All 1s
5
4
3
2
1
0
RXPOL
SCRXD
From TXD Pin
or Transmitter
Loop
Control
Data
Recovery
H
RE
RAF
MSB
LOOPS
RSRC
FE
M
WAKE
ILT
PE
PT
Wakeup
Logic
NF
PE
RWU
Parity
Checking
R8
IDLE
ILIE
Idle IRQ
Start
L
RDRF/OR
IRQ
BRKDFE
Stop
Bus
Clock
Baud Divider
RDRF
OR
RIE
Break IRQ
Break
Detect Logic
BRKDIF
BRKDIE
Active Edge
Detect Logic
RXEDGIF
RXEDGIE
RX Active Edge IRQ
Figure 11-20. SCI Receiver Block Diagram
11.4.6.1
Receiver Character Length
The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI
control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in
SCI data register high (SCIDRH) is the ninth bit (bit 8).
11.4.6.2
Character Reception
During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data register
is the read-only buffer between the internal data bus and the receive shift register.
After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the
SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set,
MC9S12XDP512 Data Sheet, Rev. 2.21
502
Freescale Semiconductor