MC9S12XDP512CFU
| Model | MC9S12XDP512CFU |
| Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
| PDF file | Total 1348 pages (File size: 8M) |
| Chip Manufacturer | PHILIPS |
23.0.5.31 Port M Input Register (PTIM)
7
6
5
4
3
2
1
0
R
W
Reset
1
PTIM7
PTIM6
PTIM5
PTIM4
PTIM3
PTIM2
PTIM1
PTIM0
—
—
—
—
—
—
—
—
= Unimplemented or Reserved
Figure 23-33. Port M Input Register (PTIM)
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
associated pin values.
Read: Anytime.
Write: Never, writes to this register have no effect.
This register always reads back the buffered state of the associated pins. This can also be used to
detect overload or short circuit conditions on output pins.
23.0.5.32 Port M Data Direction Register (DDRM)
7
6
5
4
3
2
1
0
R
DDRM7
W
Reset
0
0
0
0
0
0
0
0
DDRM6
DDRM5
DDRM4
DDRM3
DDRM2
DDRM1
DDRM0
Figure 23-34. Port M Data Direction Register (DDRM)
Read: Anytime.
Write: Anytime.
This register configures each port M pin as either input or output.
The CAN forces the I/O state to be an output for each port line associated with an enabled output
(TXCAN). also forces the I/O state to be an input for each port line associated with an enabled
input (RXCAN). In those cases the data direction bits will not change.
The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral
module is disabled.
Table 23-33. DDRM Field Descriptions
Field
7–0
DDRM[7:0]
Description
Data Direction Port M
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note:
Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PTM or PTIM registers, when changing the DDRM register.
