MC9S12XDP512CFU
Model | MC9S12XDP512CFU |
Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
PDF file | Total 1348 pages (File size: 8M) |
Chip Manufacturer | PHILIPS |
Chapter 17 Memory Mapping Control (S12XMMCV2)
Global Address [22:0]
0
0
0
Bit19 Bit18
Bit12 Bit11
Bit0
RPAGE Register [7:0]
Address [11:0]
Address: CPU Local Address
or BDM Local Address
Figure 17-12. RPAGE Address Mapping
NOTE
Because RAM page 0 has the same global address as the register space, it is
possible to write to registers through the RAM space when RPAGE = $00.
Table 17-11. RPAGE Field Descriptions
Field
7–0
RP[7:0]
Description
RAM Page Index Bits 7–0
— These page index bits are used to select which of the 256 RAM array pages is to
be accessed in the RAM Page Window.
The reset value of $FD ensures that there is a linear RAM space available between addresses $1000 and
$3FFF out of reset.
The fixed 4K page from $2000–$2FFF of RAM is equivalent to page 254 (page number $FE).
The fixed 4K page from $3000–$3FFF of RAM is equivalent to page 255 (page number $FF).
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
625