MC9S12XDP512CFU
Model | MC9S12XDP512CFU |
Description | 16-BIT, FLASH, 40MHz, MICROCONTROLLER, PQFP80 |
PDF file | Total 1348 pages (File size: 8M) |
Chip Manufacturer | PHILIPS |
Chapter 6 XGATE (S12XGATEV2)
AND
Operation
Logical AND
AND
RS1 & RS2
⇒
RD
RD
&
IMM16
⇒
RD (translates to ANDL RD, #IMM16[7:0]; ANDH RD, #IMM16[15:8])
Performs a bit wise logical AND of two 16 bit values and stores the result in the destination register RD.
Remark: There is no complement to the BITH and BITL functions. This can be imitated by using R0 as a
destination register. AND R0, RS1, RS2 performs a bit wise test without storing a result.
CCR Effects
N
∆
N:
Z:
V:
C:
Z
∆
V
0
C
—
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Refer to ANDH instruction for #IMM16 operations.
0; cleared.
Not affected.
Code and CPU Cycles
Source Form
AND RD, RS1, RS2
AND RD, #IMM16
Address
Mode
TRI
IMM8
IMM8
0
1
1
0
0
0
0
0
0
1
0
0
0
0
1
Machine Code
RD
RD
RD
RS1
RS2
IMM16[7:0]
IMM16[15:8]
0
0
Cycles
P
P
P
MC9S12XDP512 Data Sheet, Rev. 2.21
220
Freescale Semiconductor